new product r03ds0019ej0100 rev.1.00 2011.09.05 page 1 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 8-bit 8ch d/a converter with buffer amplifiers r2a20168np/sa/sp block diagram features description ? guarantee nonlinearity error : +/-1.0lsb, di fferential nonlinearity error : +/-0.7lsb ? data transfer format: 12-bit serial data input type by 3 wire ( di, sck, ld ) ? output buffer op-amps: operable over entire voltage range from almost ground to vcc ( 0 to 5v ) ? very small size package line-up: qfn-16(pin pitch: 0.5mm), tssop-16(pin pitch 0.65mm) the r2a20168 is an integrated circuit semiconductor of cmos structure with 8 channels of built in d/a unnecessary and enabling configuration of a system with few component parts. serial data transfer type input can easily be used through a combination of three lines: di, clk, and ld. outputs incorporate buffer op-amps that have a driv e capacity of 1 ma or above for both sink source, and can operate over the entire voltage range from almost ground to vcc ( 0 to 5v ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. very small qfn package is added to lineup. it is suitable for a small mounting and reduces the mounting area. ? conversion from digital data to analog control data for home-use and industrial equipment. ? signal gain control or automatic adjustment of lcd-tv, pdp-tv or lcd display-monitor. ? blurring correction cont rol or various control of the interchangeable lens of digital still camera. ? automatic adjustment by combination with microcomputer and eeprom. (substitution of half fixed resistance) application number for sop/tssop package number for qfn package 16 9 12 8 channel decoder 15 gnd ld vcc ao1 1 v refl 8 v refu 10 ao8 8-bit upper segment r-2r 13 246578 2 ao2 3 ao3 4 ao4 5 ao5 6 ao6 7 ao7 10 13 16 1 2 3 4 5 8 6 15 7 14 12-bit shift register 13 14 clk di 11 do d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 11 9 12 18 power on reset 8-bit upper segment r-2r 8 8-bit latch 8?bit latch
new product r2a20168np/sa/sp page 2 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 pin description pin arrangement [tssop /sop] [qfn] ao6 6 4 ao5 5 3 8-bit resolution d/a converter output terminals (after power on, all channels are reset and dac data 00h is output.) ao4 4 2 ao7 7 5 function symbol pin no. load terminal (when high level is input to ld terminal, value in 12-bit shift register is loaded into decoder and 8-bit latch.) ld 12 10 serial data output terminal (data is sequentially output from the msb bit.) do 11 9 power supply terminal vcc 9 7 gnd terminal gnd 16 14 d/a converter upper reference voltage input terminal v refu 8 6 1 10 3 2 15 13 14 ao8 8 d/a converter lower reference voltage input terminal v refl 15 ao3 1 ao2 16 ao1 13 serial clock input terminal (input signal from di terminal is input to 12-bit shift register at rise of serial clock.) clk 11 serial data input terminal. ( input serial data with a 12-bit data length ) di 12 R2A20168SA/sp 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r2a20168np (top view) R2A20168SA/sp (top view) 12 11 10 9 1 2 3 4 outline: pwqn0016kb-a [np] 5 6 7 8 16 15 14 13 r2a20168np outline: ptsp0016jb-a [sa] prsp0016dh-b [sp] ao2 ao3 ao4 ld do ao8 vcc ao5 ao6 ao7 clk di ao1 gnd v refl v refu ao2 ao3 gnd ao1 di clk ao4 ao5 ao6 ao7 ld do ao8 vcc v refl v refu
new product r2a20168np/sa/sp page 3 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 absolute maximum ratings mw/deg 7.25(np) / 3.75(sa) / 7.5(sp) ta> +25deg k theta thermal derating factor tstg topr pd vo vin i ao v refl v refu vcc symbol ta= +85deg continuous conditions v -0.3 to +6.5 d/a converter upper reference voltage v -0.3 to +6.5 d/a converter lower reference voltage ma -2.0 to +2.0 buffer amplifier output current storage temperature operating temperature power dissipation output voltage input voltage supply voltage item -40 to +125 -30 to +85 290(np) / 150(sa) / 300(sp) -0.3 to vcc+0.3 <+6.5 -0.3 to vcc+0.3 <+6.5 -0.3 to +6.5 ratings v v v mw deg deg unit electrical characteristics vcc < 0.1v vcc = 0 to 2.7v vcc = 0 to 2.7v i oh = -400a vcc < 4.0v, i ol = 1.5ma 4.0v < vcc, i ol = 2.0ma v in = 0 to vcc clk =1mhz, vcc =5v, i ao =0a test conditions v 0.4 - - v - - vcc ? 0.4 v oh output high voltage s - - 100 t r vcc supply voltage rise time *1 v 1.9 1.5 - vcc por internal reset operating voltage *1 v - - 0.8vcc v ih input high voltage ms - - 1 t por power supply restart interval (power supply off ? on) *1 v 0.4 - - v ol output low voltage v 0.2vcc - - v il input low voltage a 10 - -10 i ilk input leak current ma 1.2 0.4 - icc supply current v 5.5 5.0 2.7 vcc supply voltage unit max typ min symbol item limits *1 : when power supply is turned on, internal circuit is initialized by power on reset circuit. but, if re-powered on quickly, initialize is not operate. so, keep the time period of re-powered on (t por ). vcc internal reset signal t por tr vcc < 0.1v (equivalent to tr vcc ) vcc por resetting period gnd gnd resetting period ? digital part ? ( vcc, v refu = +5v +/-10%, vcc>v refu , gnd,v refl =0v, ta= -30 to +85deg, unless otherwise noted ) (ta= +25deg unless otherwise noted)
new product r2a20168np/sa/sp page 4 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 v refu = 4.79v, v refl = 0.95v, vcc = 5.5v (15mv/lsb), without load (i ao =0a) upper side saturation voltage = 0.3v, lower side saturation voltage = 0.2v i ao = +/- 500 a i ao = +/- 100 a v refu =5v, v refl =0v, i ao =0a, data condition: at maximum current test conditions lsb 0.7 - -0.7 s dl differential nonlinearity lsb 1.0 - -1.0 s l nonlinearity lsb 2.0 - -2.0 s zero zero code error lsb 2.0 - -2.0 s full full scale error ohm - 5.0 - ro buffer amplifier output impedance f 0.1 - - co output capacitive load v vcc ? 0.2 - 0.2 ma 1.0 - -1.0 i ao buffer amplifier output drive range v vcc ? 0.1 - 0.1 v ao buffer amplifier output voltage range v 0.3vcc - gnd v refl d/a converter lower reference voltage range *2 v vcc - 0.7vcc v refu d/a converter upper reference voltage range *2 ma 2.0 1.0 - i refu current dissipation unit max typ min symbol item limits ? analog part ? ( vcc, v refu = +5v +/-10%, vcc>v refu , gnd,v refl =0v, ta= -30 to +85deg, unless otherwise noted ) *2 : the output does not necessary be the va lue with the reference voltage setting range. the output value is determined by the buffer amplifier output voltage range (v ao ).
new product r2a20168np/sa/sp page 5 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 ac characteristics timing chart clk t cr t cf t ckh t ckl t dch t chd t chl t ldh t ldc t ldd di ld d/a output t do do output ( vcc,v refu = +5v +/-10%, vcc ? v refu , gnd=v refl = 0v, ta = -30 to +85deg, unless otherwise noted ) (note) timing chart above is a schematic repr esentation of the timing of each signal type. clk signal input is high or low regardless, ld signal high input is enabled. t ldd t do t ldh t ldc t chl t chd t dch t cf t cr t ckh t ckl f clk symbol mhz 10 1.0 - clock frequency ns 50 - -10 c l < 100 pf data output delay time ta=25deg, c l <100pf, v ao : 0.5 ? ? 4.5v, the time until the output becomes the final value of 1/2 lsb. test conditions d/a output settling time ld high pulse width ld hold time ld setup time data hold time data setup time clock fall time clock rise time clock high pulse width clock low pulse width item s ns ns ns ns ns ns ns ns ns unit typ min - 40 40 40 30 4 - - 40 40 limits - - - - - - - - - - - - 200 - - 200 - - 150 - max
new product r2a20168np/sa/sp page 6 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 digital data format last lsb d9d8 d5 d6 d11 d10 d7 d4d3d2d1d0 (v refu ?v refl ) / 256 x 255 + v refl 11111110 1 : 0 0 0 0 d2 1 : 0 0 0 0 d3 1 : 0 0 0 0 d4 1 : 1 1 0 0 d1 v refu 111 1 : ::: : (v refu ?v refl ) / 256 x 4 + v refl 000 1 (v refu ?v refl ) / 256 x 3 + v refl 000 0 (v refu ?v refl ) / 256 x 2 + v refl 000 1 (v refu ?v refl ) / 256 x 1 + v refl 000 0 d/a output d7d6d5 d0 first msb dac data channel select data channel select data ao5 select 1010 ao6 select 0110 ao7 select 1110 ao8 select 0001 : :::: don?t care 0000 ao1 select 1000 ao2 select 0100 ao3 select 1100 don?t care 1001 ao4 select 0010 1 1 d9 1 1 d8 don?t care 11 don?t care 01 chanel selection d11 d10 dac data
new product r2a20168np/sa/sp page 7 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 precaution for use analog voltage output 10f + ao1 ao2 gnd vcc 10f + 10f + ao7 ao8 standard application circuit ld clk di mcu data timing chart ( model ) di ld d/a output d2 d9 d10 d11 clk d8 d7 d1 d0 msb lsb whether clk input is ?h? or ?l?, high level input of ld signal is recognized. ? there are three terminals (vcc, v refu , v refl ) that should be impressed a constant voltage. when ripple or spike noise is input to this terminal, there is fear that the accuracy of d/a conversion becomes lower and this ic malfunction. so, when use this ic, please connect capacitor between these terminals (vcc, v refu , v refl ) and gnd for stable d/a conversion. ? this ic?s output amplifier has an advantage to capacit ive load, so, it?s no problem at device action when connect capacitor ( 0.1f max ) among output to gnd for every noise elimination. v refl v refu
new product r2a20168np/sa/sp page 8 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 package dimensions ptsp0016jb-a [sa] prsp0016dh-b [sp]
new product r2a20168np/sa/sp page 9 of 9 r03ds0019ej0100 rev.1.00 2011.09.05 pwqn0016kb-a [np] ordering information embossed taping/2,000 pcs. sp prsp0016dh-b sop-16 r2a20168sp embossed taping/2,000 pcs. sa rtsp0016jb-a tssop-16 R2A20168SA embossed taping/3,000 pcs. np pwqn0016kb-a qfn-16 r2a20168np packing/quantity package type no. package code package name order part no.
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